1. Field of the Invention
The present invention relates to a method for fabricating a cell transistor of a flash memory, and more particularly, to a method for fabricating a cell transistor of a flash memory to prevent the decrease of yield by removing the residue generated when etching a gate electrode.
2. Discussion of the Related Art
Recently, an EEPROM (Electrically Erasable Programmable Read-Only Memory) type flash memory is widely used for a digital camera, a mobile phone, etc. The EEPROM type flash memory may completely erase data from memory cells, or may erase data from memory cells by each unit sector.
In the EEPROM type flash memory, on a programming mode, a channel hot electron generates at the side of drain, and the channel hot electron is stored in a floating gate, whereby a threshold voltage of a cell transistor increases. In the meantime, on an erasing mode of the EEPROM type flash memory, a high voltage is generated between the floating gate and source/substrate, and the channel hot electron stored in the floating gate is discharged, thereby lowering the threshold voltage of the cell transistor.
FIG. 1 is a cross sectional view of illustrating a cell transistor of a flash memory according to the related art. Referring to FIG. 1, a cell transistor of a flash memory according to the related art is comprised of a semiconductor substrate 10, a device isolation film 12, a tunnel oxide layer 16, a floating gate 18, a gate insulating layer 20, a control gate 22, and source and drain regions 26. At this time, the semiconductor substrate 10 is formed of a silicon substrate, and the device isolation film 12 of an STI (Shallow Trench Isolation) structure is formed on the semiconductor substrate 10. Then, the tunnel oxide layer 16, the floating gate 18, the gate insulating layer 20 and the control gate 22 are sequentially stacked on the semiconductor substrate 10 in correspondence with the predetermined portion between the device isolation films 12. Also, the source and drain regions 26 are formed in the semiconductor substrate 10 at both sides of the floating gate 18.
In addition, an insulating interlayer 30 is formed on an entire surface of the cell transistor. Also, a contact electrode 32 and a line 34 are connected with the source and drain regions 26 through a contact hole of the insulating interlayer 30.
Next, a well 14 is formed in the semiconductor substrate 10 between the device isolation films 12. Then, spacers 24 are formed at the sidewalls of the control gate 22 and the tunnel oxide layer 16, wherein the spacers are formed of an insulating material. Also, a metal silicide layer 28 of tungsten silicide WSi is formed on the control gate 22 and the source and drain regions 22.
According to the trend toward the high-integration semiconductor device, the device isolation film 12 prefers an STI (Shallow Trench Isolation) structure to an LOCOS (LOCal Oxidation of Silicon) structure. In case the device isolation film is formed in the STI structure, it is possible to decrease the width of the device isolation film.
FIG. 2 is a flow chart of illustrating the process for fabricating the device isolation film and the gates in the cell transistor of the flash memory according to the related art.
FIG. 3A to FIG. 3E are cross sectional views of the process for fabricating the device isolation film and the gates in the cell transistor of the flash memory according to the related art.
The device isolation film 12 of STI structure and the gates 18 and 22 in the cell transistor of the flash memory according to the related art are fabricated in the following process.
Referring to FIG. 3A, an STI moat pattern 15 is formed in the semiconductor substrate 10. Then, the semiconductor substrate 10 exposed by the STI moat pattern 15 is etched, thereby forming a shallow trench 13 (S10). At this time, the STI moat pattern 15 is formed of a silicon nitride layer Si3N4. In addition, a silicon oxide layer SiO2 may be additionally formed below the STI moat pattern 15, wherein the silicon oxide layer functions as a pad.
Referring to FIG. 3B, the shallow trench 13 is gap-filled by HDP (High Density Plasma) process, whereby the shallow trench 13 is filled with an insulating layer 17 such as silicon oxide SiO2 or TEOS (Tetraethylorthosilicate).
Referring to FIG. 3C, the gap-fill insulating layer 17 is etched by CMP (Chemical Mechanical Polishing) when exposing the STI moat pattern 15, thereby planarizing the surface of the insulating layer.
Referring to FIG. 3D, the STI moat pattern 15 is removed with phosphoric acid H3PO4 (S14 to S16) to form the device isolation films 12.
Referring to FIG. 3E, the tunnel oxide layer 16 is formed on the semiconductor substrate 10 in correspondence with the predetermined portion between the device isolation films 12. Thereon, after forming a conductive layer for the floating gate, for example, doped polysilicon, the gate insulating layer of ONO (oxide-nitride-oxide) is formed, and then a conductor layer for the control gate, for example, doped polysilicon, is formed in sequence. Then, the gate electrode of the cell transistor in the flash memory is patterned in a dry-etching method of using a gate mask (S18). That is, the control gate 22 is formed by patterning the upper doped polysilicon, and the gate insulating layer 20 is patterned under the control gate 22. Then, the floating gate 18 is formed by patterning the lower doped polysilicon.
If the gap-filling process for the shallow trench is performed by HDP when fabricating the device isolation film according to the related art, the mouse bite 11 may be generated in the upper edge of the shallow trench due to the characteristics of HDP performing the deposition and etching process together, as shown in FIG. 4. On the etching of HDP, there is the layer having the relatively large etching ratio than the remaining portions. Thus, the negative sloping surface is formed in the upper edge of the device isolation film of STI structure. As a result, as shown in FIG. 5, the etching residue (a) of polysilicon remains on the patterning process of the gate electrode due to the negative sloping surface.